An active area of a field-effect transistor (FET) is formed in a single crystalline semiconductor substrate such as a silicon wafer. The active area includes two doped impurity regions defining a first and a second source/drain region of the field-effect transistor and a channel region between the first and the second source/drain region. The first and the second source/drain region have a first conductivity type. The channel region is not doped or is of a second conductivity type, which is the opposite of the first conductivity type. The source/drain regions and the channel region adjoin a substrate surface of the semiconductor substrate.
A gate electrode is disposed on the substrate surface above the channel region. A gate dielectric insulates the gate electrode from the channel region. An electric potential applied to the gate electrode controls by capacitive coupling a charge carrier distribution in the adjoining channel section.
Lightly doped sections of the source/drain regions are aligned to the opposing vertical sidewalls of the gate electrode. Heavily doped sections of the source/drain regions provide low resistivity contact regions for to connect the respective source/drain region to another electrical circuit that is provided in or above the semiconductor substrate. For proper operation of the FET, especially of a FET realized for DMOS applications, the heavily doped sections of the source/drain regions must be formed in a defined distance to the opposing vertical sidewalls of the gate electrode.
Sidewall spacers are commonly used to define an implant mask for the definition of the heavily doped sections of the source/drain regions. Further, sidewall spacers are used to insulate the gate electrode of a FET from contact structures accessing the source/drain regions.
Spacer structures like sidewall spacers are used in a multitude of patterning methods that provide secondary structures in a defined distance to primary structures wherein the distance between the two structures cannot be controlled sufficiently by lithographic patterning methods due to their sub-lithographic footprint and the existing topography.
In connection with the formation of field effect transistors a sidewall spacer is commonly a small strip of silicon nitride or silicon dioxide, which extends on opposing sides of the polysilicon gate electrode. The sidewall spacer acts as an implant mask and shields the underlying lightly doped sections of the source/drain regions from the subsequent heavy implant dose for providing the heavily doped contact sections of the source/drain regions.
The sidewall spacer is usually formed from a conformal layer of deposited oxide or nitride or a combination of these. An anisotropic etch is performed, wherein horizontal sections of the conformal layer are removed. The anisotropic etch is or comprises a sputter etch and removes the deposited material in a top-bottom direction. The etch process is stopped after removal of the horizontal sections of the conformal layer, such that residues of the conformal layer form sidewall spacers on the vertical sidewalls.
Sidewall spacer control deteriorates with increasing thickness of the sidewall spacer with reference to the height of the gate electrode. The yield of a sputter etch process depends on the inclination of the etched surface to the sputter beam. Regarding the sputter etch processes used in connection with the formation of sidewall spacers, the yield is high for an inclination of the etched surface of about 30 to 40 degrees towards the sputter beam. Starting from a rectangular structure with a horizontal surface and a vertical surface forming a right-angled edge, an etch process with a sputter etch component therefore tends to generate an oblique surface having an inclination of about 30 to 40 degrees to the sputter beam with continuing process time. With increasing thickness of the conformal layer with respect to the height of the gate electrode, an anisotropic etch process therefore results more in a triangular cross-section of the sidewall spacer than in a rectangular cross-section, wherein an incline angle between the outer vertical sidewall of the sidewall spacer and the substrate surface is about 50 to 60 degrees.
As a consequence, the width of the sidewall spacer on the base near the substrate surface depends on the height of the gate electrode. For voltage differences between the gate electrode and the heavily doped section of the source/drain regions of above 10 V a distance between the heavily doped source/drain region and the gate electrode of about 180 to 220 nm is required. For typical heights of the gate electrode stack of 200 nm the usual spacer technology does not reliably meet the requirements on spacer conformity.
Additionally, at the edge of the sidewall spacer the underlying etch stop liner suffers from defect issues due to the requirement of an over-etch of the conformal layer in order to ensure complete removal from horizontal sections.
The spacer width is governed therefore by the profile of the gate electrode, the thickness control, and the conformity of the spacer dielectric deposition as well as the ratio of an isotropic component to the anisotropic component of the spacer etch. Improved control of all factors that can affect the spacer width, such as spacer dielectric deposition and etch end-point detection, will be needed to ensure sufficient reproducibility.
Therefore a need exists for sidewall spacers and for methods of forming such sidewall spacers, which are independent from process deviations. Providing such spacer structures and providing such methods for forming such sidewall spacers make feasible new advantageous methods of forming field effect transistors and new advantageous patterning methods.